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STLC4550
Single chip 802.11b/g WLAN radio
DATA BRIEF
Features

Extremely small footprint Ultra Low Power consumption Fully compliant with the IEEE 802.11b and 802.11g WLAN standards Support for 54, 48, 36, 24, 18, 12, 9, and 6Mbps OFDM, 11 and 5.5Mbps CCK and legacy 2 and 1Mbps data rates Single Chip 802.11b/g WLAN solution with Fully integrated: - Zero IF (ZIF) transceiver, - Voltage Controlled Oscillator (VCO), - High-Speed A/ D and D/A Converters, - Radio Power Management Unit (PMU), - OFDM and CCK baseband processor, - ARM9 Media Access Controller (MAC), - SPI serial host interface - SDIO (4-bit) serial host interface - Passive components integration - PA bias control - Flexible integrated Power Management Unit - Glueless FEM interface Intelligent Power Control, Including 802.11 Power Save Mode Fully integrated Bluetooth coexistence
LFBGA240 (8.5x8x1.4mm)
Description
The STLC4550 is a single chip 802.11b/g WLAN radio for embedded, low-power and very small form factor mobile applications. The product conforms to the IEEE 802.11b and 802.11g protocols operating in the 2.45GHz ISM frequency band supporting OFDM data rates of 54, 48, 36, 24, 18, 12, 9, and 6Mbps as well as CCK data rates of 11 and 5.5Mbps and legacy data rates of 2 and 1Mbps. The STLC4550 is a fully integrated wireless radio including a ZIF transceiver, RDocRev1F Synthesizer/VCO, high-speed data converters, an OFDM/CCK digital baseband processor, an ARM9-based MAC and a complete Power Management Unit with integrated PA bias control. In addition some passive components are integrated further reducing the overall reference design cost and size. An external FEM completes a highly integrated chip set solution. Host control is provided by a flexible SPI or SDIO serial interface. The SPI interface supports a maximum clock rate of 48MHz whereas the SDIO supports a maximum clock rate of xxMHz. For maximum flexibility, the STLC4550 accepts system reference clock frequencies of 19.2, 26, 38.4 and 40MHz. A reference design evaluation platform of hardware and software is provided to system integrators to rapidly enable wireless connectivity to mobile platforms.
Applications

Cellular Phones Personal Digital Assistants (PDA) Portable Computers Hand-held Data Transfer Devices Cameras Computer Peripherals Cable Replacement
Order codes
Part number STLC4550 Temp range, C -30 to 85C Package LFBGA240- (8.5x8x1.4mm) Packing Tray
February 2006
DocRev1
1/5
www.st.com 5
For further information contact your local STMicroelectronics sales office.
1
2/5
VDD_BIAS VDD_CORE 1.2V 4 22uF
D D
Figure 1.
7.0pF 2.8V 2 4.7uF 0.1uF 4.7uF 0.1uF 4.7uF 0.1uF
A A D D A A
VDD_VCO VDD_QLO 1.8V VDDA 1.8V 4 6 1.8V VDDD
4.7uH
A A A
1M
A
PMU_RSET PMU_CREF Power Management Unit (PMU) DGND
D
0.1uF 2x 6x 3.6V 6 VBATT 4x 4x
4.7uF
0.1uF
Antenna 1uF LNA_IN+ 7.0pF Balun LNA_IN3.3pF 0.1uF VCO_CAP VDD_VCO 6.49K VCO_LOOP 68pF TX_OUT Baseband Processor (BBP) OFDM/CCK Modulation High-Speed Data Converters 4700pF RF ZIF Section: 3.3pF
Block diagram & Application circuit
BPF
SPI_CSX SPI_CLK SPI_DIN SPI_DOUT HOST_IRQ VIO POWER_UP SLEEP_CLK OSC_EN ARM9 WEP REF_CLK 1000pF TX_CONF Media Access Controller (MAC) Host CPU RF VCO RX Downconverter TX Upconverter Baseband Filters
7.0pF
RF FEM (PA Swiches)
Block diagram & Application circuit
Block Diagram and Application Circuit (Standard Front End Module)
DocRev1
PA_DET PA_BIAS PA_RREF 20K
A
RF_ACTIVE STATUS FREQ
Bluetooth Device
7.0pF
7.0pF
ANTSEL+/TRSW+/Switch Control
LOOP44
1000pF 1.2K 82pF
A
A
D
Note: Refer to evaluation platform schematics for optimized component values.
STLC4550
STLC4550
Package Information
2
Package Information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA240 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 7.85 0.25 8.35 0.3 8.5 7.5 8 7 0.5 0.5 0.08 0.15 0.05 8.15 0.309 0.15 1.065 0.28 0.8 0.35 8.65 0.010 0.329 0.012 0.335 0.295 0.315 0.276 0.020 0.020 0.003 0.006 0.002 0.321 TYP. MAX. 1.4 0.006 0.042 0.011 0.031 0.014 0.341 MIN. TYP. MAX. 0.055 inch
OUTLINE AND MECHANICAL DATA
Body: 8.5 x 8 x 1.4mm
LFBGA240 Low Profile Ball Grid Array
7870466 A
DocRev1
3/5
Revision history
STLC4550
3
Revision history
Table 1.
Date 06-Feb-2006
Document revision history
Revision 1 Initial release. Changes
4/5
DocRev1
STLC4550
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